1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device, and more specifically, it relates to a process for manufacturing a capacity element of DRAM in which a tantalum oxide film is used as a capacity insulating film.
2. Description of the Prior Art
With regard to capacity elements of very large scale integrated circuit (VLSI) memory devices, since the development of 256M bit DRAM, the employment of capacity insulating films having a high dielectric constant which can increase a capacity value per unit area has been investigated. Among such capacity insulating films, a tantalum oxide film obtained by chemical vapor deposition (CVD) has a high dielectric constant .epsilon..sub.r of 25 to 30, which means that the tantalum oxide film possesses excellent step coverage properties. In addition, the formation of the tantalum oxide film is much easier as compared with other insulating films having a high dielectric constant. For these reasons, the tantalum oxide film has been positively researched.
An example of such a memory devices is illustrated in FIG. 1 which is taken from my prior U.S. Pat. No. 5,352,623. This FIG. 1 corresponds to FIG. 2 of the '623 patent and shows a pair of memory cells, for simplicity, each constituted by a transistor 50 having active regions in the first P-well 43A, although a large number of memory cells are formed within the first P-well 43A. The pair of memory cells comprise n-type regions 51 and 51A as source and drain regions of the pair of transistors 50 and gate electrodes 55 composed of polysilicon 53 and silicide 54. The pair of transistors 50 are covered by a first interlayer insulating film 47 through which a contact hole 58 filled with a contact connecting a bit line 56 with the n-type region 51. i.e., one of the source and drain regions of and common to the pair of transistors 50. A second interlayer insulating film 48 is formed to cover the bit line 56, following which a pair of stacked capacitor elements surrounded in the drawing by a dotted line 70 are formed on the second interlayer insulating film 48.
Each of the stacked capacitor elements comprises a lower capacitor electrode 2 made of poysilicon, a tantalum oxide film 11 as a dielectric film of the capacitor element and an upper capacitor electrode 3. The lower capacitor electrodes 2 are connected to the respective n-type regions 51A, i.e. the other off the source and drain regions of the transistors 50, via respective contact holes 57 formed in the first and second interlayer insulating films 47 and 48. The upper capacitor electrode 3 is common to the capacitor elements of the pair of memory cells, extending on the tantalum oxide film 11 and the second interlayer insulating film 48.
The upper capacitor electrode 3 is electrically connected via a through-hole 67 to an aluminum electrode 71A maintained at a fixed potential, such as a ground potential, and formed on a third interlayer insulating film 49. The aluminium electrode 71A comprises an aluminum layer and a titanium nitride film 72 underlying the aluminum layer. The through-hole 67 is filled with a tungsten plug 73 and a titanium nitride film 72 covering the tungsten plug 73.
A transistor 60 forming a peripheral circuit of the memory device is shown as having n-type regions 51B in the second P-well 43B, a gate insulating film 52 formed on the P-well 43B, and a gate electrode 55 composed of a polysilicon film 53 and an silicide film 54 and formed on the gate insulating film 52. Aluminum electrode 71B for the transistor 60 is connected to one of the source and drain regions 51B via a contact hole 68 formed through the first, second and third insulating films 47, 48 and 49 and filled with a tungsten plug 73 and a titanium nitride film 72 formed thereon. Another gate electrode 55 of a transistor of the peripheral circuit not shown in the drawing is connected to the aluminum electrode 71C.
FIG. 10 is a sectional view of a process for manufacturing a capacity element for a cell of DRAM, and with reference to FIG. 10, reference will be made to a conventional method for manufacturing a stack type capacity element for DRAM in which the tantalum oxide film is used as the capacity insulating film.
First, a transistor is formed on the surface of a P-type silicon substrate, and this transistor is then covered with an interlayer insulating film 47. Next, a contact hole 58 is formed through the interlayer insulating film 47 so as to reach one of the N-type source drain regions of the transistor. A bit line 56 connected to this N-type sourcedrain region via the contact hole 58 is formed on the surface of the interlayer insulating film 47. Then, an interlayer insulating film 48 is formed so as to cover the surface of the interlayer insulating film 47 inclusive of the bit line 56.
On such a structure, a contact hole 57 is formed so as to reach the other N-type source-drain regions of the transistor through the interlayer insulating films 48, 47. Then, a polycrystal silicon film doped with phosphorus is formed all over the structure, and this polycrystal silicon film is patterned to obtain a capacity lower electrode 2. Next, a tantalum oxide film 11 is formed on the surface of the interlayer insulating film 48 inclusive of the capacity lower electrode 2 by vacuum vapor deposition using a pentaethoxytantalum [Ta(OC.sub.2 H.sub.5).sub.5 ] gas as an organic material and oxygen [FIG. 10 (a)]. Afterward, in order to improve the leakage current properties of this tantalum oxide film 11, high temperature heat treatment is carried out in an oxygen atmosphere, whereby the tantalum oxide film 11 becomes a tantalum oxide film 11B [FIG. 10 (b)]. The temperature in this heat treatment is usually in the range of 700.degree. to 900.degree. C. In succession, a capacity upper electrode 3 is formed [FIG. 10 (c)]. As this upper electrode 3, a tungsten film or the like is used.